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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER WRITE Command
MODE REGISTER WRITE Command
The MODE REGISTER WRITE (MRW) command is used to write configuration data to
the mode registers. The MRW command is initiated with CS# LOW, CA0 LOW, CA1 LOW,
CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register is selected by
CA1f–CA0f, CA9r–CA4r. The data to be written to the mode register is contained in
CA9f–CA2f. The MRW command period is defined by t MRW. MRWs to read-only regis-
ters have no impact on the functionality of the device.
MRW can only be issued when all banks are in the idle precharge state. One method of
ensuring that the banks are in this state is to issue a PRECHARGE ALL command.
Figure 66: MODE REGISTER WRITE Timing – RL = 3, t MRW = 5
T0
T1
T2
Tx
Tx + 1
Tx + 2
Ty 1
Ty + 1
Ty + 2
CK#
CK
t MRW
t MRW
CA[9:0]
MR addr MR data
MR addr MR data
CMD
MRW
NOP 2
NOP 2
MRW
NOP 2
NOP 2
Valid
Notes:
1. At time Ty, the device is in the idle state.
2. Only the NOP command is supported during t MRW.
Table 48: Truth Table for MRR and MRW
Current State
All banks idle
Bank(s) active
Command
MRR
MRW
MRW (RESET)
MRR
MRW
MRW (RESET)
Intermediate State
Reading mode register, all banks idle
Writing mode register, all banks idle
Resetting, device auto initialization
Reading mode register, bank(s) idle
Not allowed
Not allowed
Next State
All banks idle
All banks idle
All banks idle
Bank(s) active
Not allowed
Not allowed
MRW RESET Command
The MRW RESET command brings the device to the device auto initialization (reset-
ting) state in the power-on initialization sequence (see 2. RESET Command under Pow-
er-Up (page 40)). The MRW RESET command can be issued from the idle state. This
command resets all mode registers to their default values. Only the NOP command is
supported during t INIT4. After MRW RESET, boot timings must be observed until the
device initialization sequence is complete and the device is in the idle state. Array data
is undefined after the MRW RESET command has completed.
For MRW RESET timing, see Figure 26 (page 42).
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
91
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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